3D Test 2010 - Call for Participation

Advance Registration Deadline Extended to October 8th!

CALL FOR PARTICIPATION

Scope -- Key Dates -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

The new 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.

Workshop Program – The workshop program contains the following elements.

Keynote address: “Testing In a New Dimension”
by Bob Patti, CTO of Tezzaron Semiconductor, USA
Invited Address: “An Integrated Approach to Design and Test of 3D ICs”
by Sanjiv Taneja, VP Front-End Design, Cadence Design Systems, USA
Various paper and invited presentation sessions
Continuous poster display and Table-Top Demos
A panel session

For the detailed version of the program, please see Advance Program section below.

Key Dates

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Advance Registration Deadline: October 8th, 2010!
Submit Poster proposals Deadline: October 15, 2010
Submit Table-Top Demo proposals Deadline: October 15, 2010
Sign up as Corporate Supporter For more information: http://3dtest.tttc-events.org

Workshop Registration

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You are invited to participate in the workshop. Participation requires registration and a registration fee. Workshop registration includes all technical sessions, Electronic Workshop Digest (containing extended abstracts, papers, slides, posters, as far as made available by their presenters), workshop reception, continental breakfast, lunch, and break refreshments. Early (discount) registration is available till October 8, 2010 via the workshop’s website (http://3dtest.tttc-events.org), on-line as well as via a fax-back from. Alternatively, register on-site during Test Week at the ITC Registration Counter at the Austin Convention Center; admission for on-site registrants is subject to availability.

Advance Program

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Thursday -- Friday

November 4, 2010 (Thursday)

4:00 PM - 5:00 PM	OPENING SESSION Moderator: Mike Ricchetti – AMD, USA
4:00 - 4:15	Welcome Address General Chair: Yervant Zorian – Virage Logic, USA Program Chair: Erik Jan Marinissen – IMEC, B
4:15 - 5:00	Keynote Address: Testing in a New Dimension Bob Patti – Tezzaron Semiconductor, USA

5:00 PM - 6:30 PM	Session 2 - 3D Design-for-Test Moderator: Craig Bullock – Texas Instruments, USA
5:00 - 5:30	Invited Address: An Integrated Approach to Design and Test of 3D ICs Sanjiv Taneja – Cadence Design Systems, US
5:30 - 5:45	Embedded Test Resource Partitioning for Memories in a 3D-IC Context Yervant Zorian – Synopsys, USA
5:45 - 6:00	Functional/Structural Test Boundaries for 3D-IC Rob Aitken, Teresa McLaurin – ARM, USA
6:00 - 6:15	Standardization for 3D-Testing Erik Jan Marinissen – IMEC, B
6:15 - 6:30	Mini-Panel

6:30 PM - 7:00 PM	Session 3 - Posters and Demos Posters are on display throughout the workshop.
Poster 1	Power Constrained Test Scheduling for 3D Stacked Chips Breeta SenGupta, Urban Ingelsson, Erik Larsson – Linköping University, SE
Poster 2	Parallel Test of Identical Cores Using Test Elevators in 3D Circuits Alberto Bosio, Giorgio di Natale – LIRMM, FR
Poster 3	Interconnect Built-In Self-Repair and Adaptive Serialization (I-BIRAS) for 3D Integrated Systems Michael Nicolaidis, Lorena Anghel, Vladimir Pasca – TIMA, FR
Poster 4	Die-Wrapper Optimization for 3D Stacked ICs Brandon Noia, Krishnendu Chakrabarty – Duke University, USA; Erik Jan Marinissen – IMEC, B
Poster 5	An IEEE Std 1500-Based 3D Design-for-Test Architecture Erik Jan Marinissen – IMEC, B; Chun-Chuan Chi – Natl. Tsing-Hua University, TW; Jouke Verbree – Delft University of Technology, NL; Mario Konijnenburg – IMEC-NL, NL
Poster 6	1149.3D?! – Leveraging Test Access Standards for 3D-SICs Adam Ley, Al Crouch – Asset Intertech, USA
Poster 7	Design and Test of 3D-MAPS, a 3D Die-Stack Many-Core Processor Dean Lewis, Michael Healy, Mohammad Hossain, Tzu-Wei Lin,Mohit Pathak, Hemant Sane, Sung Kyu Lim, Gabriel Loh, Hsien-Hsin Lee – Georgia Tech, USA
Poster 8	Wireless Wafer Test for Iterative Testing During System Assembly Z. Noun – LIRMM, FR; Philippe Cauvet – OPHTIMALIA, FR Marie-Lise Flottes, D. Andreu, Serge Bernard – LIRMM, FR
Poster 9	New Testing Technique for Copper TSV in 60GHz Wireless Applications Sukeshwar Kannan, Bruce Kim – University of Alabama, USA
Poster 10	A Wafer Ordering Heuristic for Iterative Wafer Matching in W2W 3D-SICs with Diverse Die Yields Eshan Singh – Stanford University, USA
Demo 1	IEEE 1149.1-2011, Multi-TAP iMajik and Concurrent JTAG for 3D-SICs CJ Clark – Intellitech, USA

7:00 PM - 9:00 PM WORKSHOP RECEPTION

November 5, 2010 (Friday)

7:00 AM - 8:00 AM WORKSHOP BREAKFAST

8:00 AM - 10:00 AM	Session 4 - Pre- and Post-Bond Testing Moderator: TBD
8:00 - 8:30	KGD Probing of TSVs at 40um Array Pitch Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Chris Fournier, Eric Strid – Cascade Microtech, USA
8:30 - 9:00	Sharing of Logic and Test TSVs for Testing of 3DICs Shravan Garlapati, Michael S. Hsiao, Leylay Nazhandali – Virginia Tech, USA
9:00 - 9:30	Applying Electric Fault Simulation for Deriving Tests for TSVs Matthias Gulbins, Fabian Hopsch, Peter Schneider, Bernd Straube, Wolfgang Vermeiren – Fraunhofer IIS/EAS, D
9:30 - 10:00	Impact of Various Test Flows on the Cost in 3D D2W Stacking Mottaqiallah Taouil, Said Hamdioui – Delft Univ. of Technology, NL; Erik Jan Marinissen – IMEC, B

10:00 AM - 10:30 AM	Session 5 - Posters and Demos Posters are on display throughout the workshop (see listing above). Coffee & Tea Provided

10:30 AM - 12:00 PM	Session 6 - TSV Testing Moderator: Stephen Pateras – Mentor Graphics, USA
10:30 - 11:00	Comparing Through-Silicon Via Void/Pinhole Defect Self-Test Methods Yi Lou, Zhuo Yan, Fan Zhang, Paul Franzon – North-Carolina State Univ., USA
11:00 - 11:30	Multi-Scale Simulation and Characterization for Stress Management in 3D IC TSV-Based Integration Technology: Stress Assessment for Chip Performance Valeriy Sukharev – Mentor Graphics, USA; Ehrenfried Zschech – Fraunhofer IZFP, D
11:30 - 12:00	Electrical Tests for Three-Dimensional ICs with TSVs Chen Hao, Hung-Chih Lin, Jian-Yu Shih, Shih-Wei Li, Min-Jer Wang, Ching-Nen Peng – TSMC, TW

12:00 PM - 1:00 PM WORKSHOP LUNCHEON

1:00 PM - 1:30 PM	Session 7 - Posters and Demos Posters are on display throughout the workshop (see listing above).

1:30 PM - 2:30 PM	Session 8 - 3D-SIC Applications and Test Moderator: Samy Makar – Apple, USA
1:30 - 1:45	3D-TSV Technology: A DfT and Test Perspective Michael Laisne, Rajamani Sethuram – Qualcomm, USA
1:45 - 2:00	TBD TBD
2:00 - 2:15	Wide-IO 3D for Multimedia Application Processors: Operational Nightmare? Stephane Lecomte – ST-Ericsson, USA
2:15 - 2:30	From Stacked to 3D Devices Vincent Chalendard, Olivier Alavoine, Adin Hyslop, Christophe Sucur, Jean-Pierre Gibaux – Texas Instruments, FR

2:30 PM - 4:00 PM	Session 9 - Panel Discussion: Challenges and Solutions in 3D Wafer Probing Moderator: TBD
	Panelists: John Johnson – Intel, USA Marc Loranger – FormFactor, USA Jay Orbon – Verigy, USA Dan Rishavy – TEL, USA Ken Smith – Cascade Microtech, USA

4:00 PM WORKSHOP CLOSURE

More Information

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Yervant Zorian – General Chair
Virage Logic
47100 Bayside Parkway
Fremont, CA 94538, USA
Tel.: +1 (510) 360-8035
Fax: +1 (510) 360-8078
E-mail: yervant.zorian@viragelogic.com

Erik Jan Marinissen – Program Chair
IMEC vzw
Kapeldreef 75
B-3001 Leuven, Belgium
Tel.: +32 (0)16 28-8755
Fax: +32 (0)16 28-1515
E-mail: erik.jan.marinissen@imec.be

Committees

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General Chair:
Y. Zorian – Virage Logic (US)

Program Chair:
E.J. Marinissen – IMEC (B)

Finance Chair:
Said Hamdioui – TU Delft (NL)

Publication Chair:
M. Grosso – Politecnico di Torino (I)

Publicity Chair:
F. von Trapp – 3DInCites (US)

Web Chair:
G. Jervan – Tallinn Univ. of Techn. (EE)

Local Arrangements Chair
J. Potter - Asset-Intertech (US)

Program Committee Members:
S. Adham - TSMC (CAN)
V. Agrawal - Auburn Univ. (US)
S. Bhatia - Oasys (US)
C. Bullock - Texas Instruments (US)
K. Chakrabarty - Duke Univ. (US)
S. Chakravarty - LSI (US)
V. Chickermane - Cadence (US)
E. Cormack - DfT Solutions (UK)
A. Crouch - Asset Intertech (US)
T. Eaton - Cisco Systems (US)
G. Fleeman - Advantest (US)
M.-L. Flottes - LIRMM (F)
P. Franzon - NC State Univ. (US)
M. Higgins - Analog Devices (IRL)
S.-Y. Huang - NTHU (TW)
R. Kapur - Synopsys (US)
M. Knox - IBM (US)
M. Laisne - Qualcomm (US)
P. Lebourg - ST Microelectronics (F)
S. Lecomte - ST-Ericsson (F)
H.-H. Lee - Georgia Tech (US)
D. Lefever - Advantest (US)
I. Loi - Universita di Bologna (I)
M. Loranger - FormFactor (US)
T. McLaurin - ARM (US)
N. Minas - IMEC (B)
W. Moorhead - Scanimetrics (CAN)
K. Parker - Agilent Technologies (US)
S. Pateras - Mentor Graphics (US)
B. Patti - Tezzaron Semiconductor (US)
F. Pöhl - Infineon Technologies (D)
M. Ricchetti - AMD (US)
D. Rishavy - TEL Test Systems (US)
T. Thärigen - Cascade Microtech (D)
E. Volkerink - Verigy (US)
L. Whetsel - Texas Instruments (US)
Y. Xie - Penn. State Univ. (US)
Q. Xu - Chinese Univ. Hong Kong (HK)

For more information, visit us on the web at: http://3dtest.tttc-events.org

The 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test10) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).